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DATA SHEET
MOS INTEGRATED CIRCUIT
PD3728DZ
7300 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The PD3728DZ is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The PD3728DZ has 3 rows of 7300 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge transfer register, which transfers the photo signal electrons of 7300 pixels separately in odd and even pixels. Therefore, it is suitable for 600 dpi/A3 high-speed color digital copiers and so on.
FEATURES
* Valid photocell * Photocell pitch * Line spacing * Color filter * Resolution * Data rate * Output type * Power supply * On-chip circuits : 7300 pixels x 3 : 10 m : 40 m (4 lines) Red line - Green line, Green line - Blue line : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx*hour) : 24 dot/mm A3 (297 x 420 mm) size (shorter side) : 40 MHz MAX. (20 MHz/1 output) : 2 outputs in phase/color : +12 V : Reset feed-through level clamp circuits Voltage amplifiers
7
* Drive clock level : CMOS output under 5 V operation
ORDERING INFORMATION
Part Number Package CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600))
PD3728DZ
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S15417EJ2V0DS00 (2nd edition) Date Published October 2002 NS CP (K) Printed in Japan
The mark
shows major revised points.
2001
PD3728DZ
BLOCK DIAGRAM
CLB 1L 20
GND 16
1
2
30
29
28
23
24
GND
31
VOUT2 (Blue, even)
32
D128
CCD analog shift register Transfer gate
S7299 S7300 D129 D27
GND
33
.....
S1 S2
Photocell (Blue)
.....
D134
22
TG1 (Blue)
VOUT1 (Blue, odd) GND
34 35
Transfer gate CCD analog shift register
VOUT3 36 (Green, odd)
D128 D27
CCD analog shift register Transfer gate
S7299 S7300 D129 S1 S2
.....
.....
D134
Photocell (Green)
21
TG2 (Green)
VOUT4 1 (Green, even) GND VOUT6 (Red, even) 2 3
D128
Transfer gate CCD analog shift register
CCD analog shift register Transfer gate
D129 S1 S2
GND
4
.....
.....
D134
D27
Photocell (Red)
S7299 S7300
15
TG3 (Red)
VOUT5 (Red, odd)
5
Transfer gate CCD analog shift register
GND
6
7 VOD
8
RB
9
10
13
1
14
2
2
Data Sheet S15417EJ2V0DS
PD3728DZ
PIN CONFIGURATION (Top View)
CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600)) * PD3728DZ
Output signal 4 (Green, even) VOUT4 Ground GND
1 2
1 1 1
36 35 34 33 32 31 30 29 28
Green
VOUT3 GND VOUT1 GND VOUT2 GND
CLB 1L 20
Output signal 3 (Green, odd) Ground Output signal 1 (Blue, odd) Ground Output signal 2 (Blue, even) Ground Reset feed-through level clamp clock Last stage shift register clock 1 Shift register clock 20
Output signal 6 (Red, even) VOUT6 Ground GND
3 4 5 6 7 8 9
Output signal 5 (Red, odd) VOUT5 Ground Output drain voltage Reset gate clock Shift register clock 10 GND VOD
RB 10
No connection No connection No connection Shift register clock 1 Shift register clock 2
NC NC NC
1 2
Blue
Red
10 11 12 13 14 15
7300 7300 7300
27 26 25 24 23 22 21 20 19
NC NC NC
2 1 TG1 TG2
No connection No connection No connection Shift register clock 2 Shift register clock 1 Transfer gate clock 1 (for Blue) Transfer gate clock 2 (for Green) No connection No connection
Transfer gate clock 3 (for Red) TG3 Ground No connection No connection GND NC NC
16 17 18
NC NC
Caution
Connect the No connection pins (NC) to GND.
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
10 m Blue photocell array 4 lines (40 m)
7 m
3 m
10 m
Channel stopper
10 m
Green photocell array 4 lines (40 m)
Aluminum shield
10 m
Red photocell array
Data Sheet S15417EJ2V0DS
3
PD3728DZ
ABSOLUTE MAXIMUM RATINGS (TA = +25C)
Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Reset feed-through level clamp clock voltage Transfer gate clock voltage Operating ambient temperature Storage temperature
Note
Symbol VOD V 1, V 1L, V 10, V 2, V 20 V RB V CLB V TG1 to V TG3 TA Tstg
Ratings -0.3 to +15 -0.3 to +8 -0.3 to +8 -0.3 to +8 -0.3 to +8 -25 to +60 -40 to +100
Unit V V V V V C C
Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25C)
Parameter Output drain voltage Shift register clock high level Shift register clock low level Reset gate clock high level Reset gate clock low level Reset feed-through level clamp clock high level Reset feed-through level clamp clock low level Transfer gate clock high level VOD V 1H, V 1LH, V 10H, V 2H, V 20H V 1L, V 1LL, V 10L, V 2L, V 20L V RBH V RBL V CLBH V CLBL V TG1H to V TG3H Symbol Min. 11.4 4.5 -0.3 4.5 -0.3 4.5 -0.3 4.5 Typ. 12.0 5.0 0 5.0 0 5.0 0 V 1H
Note
Max. 12.6 5.5 +0.5 5.5 +0.5 5.5 +0.5 V 1H
Note
Unit V V V V V V V V
(V 10H) Transfer gate clock low level Data rate V TG1L to V TG3L 2f RB -0.3 - 0 2
(V 10H) +0.5 40 V MHz
Note When Transfer gate clock high level (V TG1H to V TG3H) is higher than Shift register clock high level (V 1H (V 10H)), Image lag can increase. Remark Pin 9 ( 10) and pin 28 ( 20) should be open to decrease the influence of input clock noise to output signal waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so.
4
Data Sheet S15417EJ2V0DS
PD3728DZ
ELECTRICAL CHARACTERISTICS
TA = +25C, VOD = 12 V, f RB = 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 Vp-p, light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1 mm)+HA-50 (heat absorbing filter, t = 3 mm)
Parameter Saturation voltage Saturation exposure Red Green Blue Photo response non-uniformity Average dark signal
Note1
Symbol Vsat SER SEG SEB PRNU ADS1 ADS2
Note1
Test Conditions
Min. 1.5 - - - - - - - - - - 3.9 3.6 4.5
Typ. 2.0 0.35 0.39 0.31 6.0 1.0 0.5 2.0 1.0 600 0.3 5.6 5.1 6.4 2.0 1.0 5.0 20 - 98 630 540 460 1000 2000 2000 4000 +200 1.0 0.5 4.0 2.0
Max. - - - - 18.0 5.0 5.0 5.0 5.0 800 0.5 7.3 6.6 8.3 5.0 5.0 6.0 - 4.0 - - - - - - - - +500 - - - -
Unit V lx*s lx*s lx*s % mV mV mV mV mW k V/lx*s V/lx*s V/lx*s % % V ns % % nm nm nm times times times times mV mV mV mV mV
VOUT = 1.0 V Light shielding
Dark signal non-uniformity
DSNU1 DSNU2
Light shielding
Power consumption Output impedance Response Red Green Blue Image lag
Note1
PW ZO RR RG RB IL1 IL2 VOUT = 1.0 V
- - 4.0 - 0 95 - - - - - - - -500 - - - -
Offset level
Note2 Note3
VOS td RI TTE Red Green Blue VOUT = 1.0 V VOUT = 1.0 V VOUT = 1.0 V, data rate = 40 MHz
Output fall delay time Register imbalance
Total transfer efficiency Response peak
Dynamic range
Note1
DR11 DR12 DR21 DR22
Note2
Vsat/DSNU1 Vsat/DSNU2 Vsat/ bit1 Vsat/ bit2 Light shielding Light shielding, bit clamp mode (tcp = 150 ns) Light shielding, line clamp mode (t19 = 3 s)
Reset feed-through noise Random noise
Note1
RFTN
bit1 bit2 line1 line2
Notes 1. ADS1, DSNU1, IL1, DR11, DR21, bit1 and line1 show the specification of VOUT1 and VOUT2. ADS2, DSNU2, IL2, DR12, DR22, bit2 and line2 show the specification of VOUT3 to VOUT6. 2. Refer to TIMING CHART 2, 5. 3. When the fall time of 1L (t2') is the TYP. value (refer to TIMING CHART 2, 5).
Data Sheet S15417EJ2V0DS
5
PD3728DZ
INPUT PIN CAPACITANCE (TA = +25C, VOD = 12 V)
Parameter Shift register clock pin capacitance 1 Symbol C 1 Pin name Pin No. 13 23 Min. - - - - - - - - - - - - Typ. 350 350 350 350 350 350 10 10 10 100 100 100 Max. 500 500 500 500 500 500 - - - - - - Unit pF pF pF pF pF pF pF pF pF pF pF pF
1 10
9 14 24
Shift register clock pin capacitance 2
C 2
2 20
28 29 8 30 22 21 15
Last stage shift register clock pin capacitance Reset gate clock pin capacitance Reset feed-through level clamp clock pin capacitance Transfer gate clock pin capacitance
C L C RB C CLB C TG
1L RB CLB TG1 TG2 TG3
Remark Pins 13, 23 ( 1) and pin 9 ( 10) are connected each other inside of the device. Pins 14, 24 ( 2) and pin 28 ( 20) are connected each other inside of the device.
6
Data Sheet S15417EJ2V0DS
TIMING CHART 1 (Bit clamp mode, for each color)
TG1 to TG3
1 ( 10) 2 ( 20)
1L
RB
Data Sheet S15417EJ2V0DS
CLB
7425 7427 7429 7431 7433 7435 7437
Note
119 121 123 125 127 129 131 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
Note
VOUT1, 3, 5
VOUT2, 4, 6
Optical black (96 pixels)
Valid photocell (7300 pixels)
7426 7428 7430 7432 7434 7436 7438
120 122 124 126 128 130 132
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
PD3728DZ
Invaid photocell (6 pixels)
Invalid photocell (6 pixels)
Note Input the RB and CLB pulses continuously during this period, too. 7
PD3728DZ
TIMING CHART 2 (Bit clamp mode, for each color)
t1 t2
1 ( 10)
90% 10%
2 ( 20)
90% 10% 90% 10% t1' 90% 10% t5 t3 t10 t8 90% 10% td t7 t6 tcp t9 t11 t4 t2'
1L
RB
CLB
VOUT1 to VOUT6 RFTN VOS 10%
Symbol t1, t2 t1', t2' t3 t4 t5, t6 t7 t8, t9 t10 t11 tcp
Min. 0 0 17 5 0 17 0 -10 -5
Note 1 Note 2
Typ. 50 5 50 200 20 150 20 +50 +50 150
Max. - - - - - - - - - -
Unit ns ns ns ns ns ns ns ns ns ns
5
Notes 1. Min. of t10 shows that the RB and CLB overlap each other.
90% t10
RB
90%
CLB
2. Min. of t11 shows that the 1L and CLB overlap each other.
1L
90%
CLB
t11
90%
8
Data Sheet S15417EJ2V0DS
PD3728DZ
TIMING CHART 3 (Bit clamp, for each color)
t13 90% 10% t15 t16 t12 t14
TG1 to TG3
1 ( 10) 2 ( 20)
90%
1L
RB
90%
t11 90% Note1
CLB
Symbol t11 t12 t13, t14 t15, t16
Min. -5
Note 2
Typ. +50 10000 50 1000
Max. - - - -
Unit ns ns ns ns
3000 0 900
Notes 1. Input the RB and CLB pulses continuously during this period, too. 2. Min. of t11 shows that the 1L and CLB overlap each other.
90%
1L
CLB
t11
90%
Data Sheet S15417EJ2V0DS
9
PD3728DZ
1, 2 and 10, 20 cross points
1
2 V or more 2 V or more
2 10
20
2 V or more
2 V or more
1L, 20 cross points
20
2 V or more 0.5 V or more
1L
Remark Adjust cross points ( 1, 2), ( 10, 20) and ( 1L, 20) with input resistance of each pin.
10
Data Sheet S15417EJ2V0DS
TIMING CHART 4 (Line clamp mode, for each color)
TG1- TG3
1 ( 10) 2 ( 20)
1L
RB
Data Sheet S15417EJ2V0DS
CLB
7425 7427 7429 7431 7433 7435 7437
Note
119 121 123 125 127 129 131 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
Note
VOUT1, 3, 5
VOUT2, 4, 6
Optical black (96 pixels)
Valid photocell (7300 pixels)
7426 7428 7430 7432 7434 7436 7438
120 122 124 126 128 130 132
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
PD3728DZ
Invalid photocell (6 pixels)
Invalid photocell (6 pixels)
Note Set the RB pulse to high level during this period. Remark Inverse pulse of TG1 to TG3 can be used as CLB. 11
PD3728DZ
TIMING CHART 5 (Line clamp mode, for each color)
t1 t2
1 ( 10)
90% 10%
2 ( 20)
90% 10% 90% 10% t1' 90% 10% "H" t5 t3 t6 t4 t2'
1L
RB
CLB
td VOUT1 to VOUT6 RFTN VOS 10%
Symbol t1, t2 t1', t2' t3 t4 t5, t6
Min. 0 0 17 5 5
Typ. 50 5 50 200 20
Max. - - - - -
Unit ns ns ns ns ns
12
Data Sheet S15417EJ2V0DS
PD3728DZ
TIMING CHART 6 (Line clamp mode, for each color)
t13 90% 10% t15 t16 t12 t14
TG1 to TG3
1 ( 10) 2 ( 20)
90%
90%
1L
RB
Note
t17 90% 10% t20
t18
CLB
t19
t21
Symbol t12 t13, t14 t15, t16 t17, t18 t19 t20, t21
Min. 3000 0 900 100 200 0
Typ. 10000 50 1000 1000 t12 20
Max. - - - - - -
Unit ns ns ns ns ns ns
Note Set the RB pulse to high level during this period. Remark Inverse pulse of the TG1 and TG3 can be used as CLB.
1, 2, and 10, 20 cross points
1
2 V or more 2 V or more
2 10
20
2 V or more
2 V or more
1L, 20 cross points
20
2 V or more 0.5 V or more
1L
Remark Adjust cross points ( 1, 2), ( 10, 20) and ( 1L, 20) with input resistance of each pin.
Data Sheet S15417EJ2V0DS
13
PD3728DZ
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula.
PRNU (%) =
x x 100 x
x : maximum of xj - x
7300 j=1
xj
x=
7300
xj : Output voltage of valid pixel number j
VOUT
Register Dark DC level
x
x
4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
7300 j=1
dj
dj : Dark signal of valid pixel number j
ADS (mV) =
7300
14
Data Sheet S15417EJ2V0DS
PD3728DZ
5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of dj - ADS j = 1 to 7300 dj : Dark signal of valid pixel number j
VOUT ADS Register Dark DC level DSNU
6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx*s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line.
TG
Light ON OFF
VOUT V1 VOUT
IL (%) =
V1 x 100 VOUT
Data Sheet S15417EJ2V0DS
15
PD3728DZ
9. Register imbalance : RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. This is calculated by the following formula.
n
2 n RI (%) =
j=1
(V2j -1 - V2j)
1 n
j=1
2
Vj
n : Number of valid pixels Vj : Output voltage of each pixel
n
x 100
10. Total transfer efficiency : TTE The total transfer rate of CCD analog shift register. This is calculated by the following formula, it is defined by each output. TTE (%) = (1 - Vb / average output of all the valid pixels) x 100
Vb Va-1 : The last pixel output - 1 (Odd pixel: 7431st pixel) Va : The last pixel output (Odd pixel: 7433rd pixel) Vb : The spilt pixel output (Odd pixel: 7435th pixel) Va-1 Va
11. Random noise : Random noise is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). This is calculated by the following formula.
100
(mV) =
i=1
(Vi - V)
100
2
, V=
1
100
100 i = 1
Vi
Vi : A valid pixel output signal among all of the valid pixels for each color
VOUT V1 V2 line 1 line 2
V100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
...
line 100
...
16
Data Sheet S15417EJ2V0DS
PD3728DZ
STANDARD CHARACTERISTIC CURVES (Reference Value)
DARK OUTPUT TEMPERATURE CHARACTERISTIC
8 2
STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25C)
4
Relative Output Voltage Relative Output Voltage
1
2
1
0.5
0.25
0.2
0.1 0
10
20
30
40
50
0.1
1
5 Storage Time (ms)
10
Operating Ambient Temperature TA (C)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25C)
100 B
80 R
Response Ratio (%)
60 G
40
20 G B 0 400 500 600 Wavelength (nm) 700 800
Data Sheet S15417EJ2V0DS
17
PD3728DZ
APPLICATION CIRCUIT EXAMPLE
+5 V 10 +
B4
+12 V
PD3728DZ
1 2
B6
+
10 F/16 V 0.1 F
VOUT4 GND VOUT6 GND VOUT5 GND VOD
VOUT3 GND VOUT1 GND VOUT2 GND
36 35 34 33 32 31 30 29 28
B3
0.1 F 47 F/25 V
B1
+5 V
3 4
+
B2
B5
5 6 7
0.1 F 10 F/16 V 47 47 2
RB
47 2
CLB 1L 20
CLB
8 9
RB 10
10 11 12
2
NC NC NC
NC NC NC
27 26 25 24 23 22 21 20 19
2 2 2 2
13 14 15 16 17 18
2
2 2
1 2 TG3
GND NC NC
2 1 TG1 TG2
NC NC
1 TG
Caution
Connect the No connection pins (NC) to GND.
18
Data Sheet S15417EJ2V0DS
PD3728DZ
Remarks 1. Pin 9 ( 10) and pin 28 ( 20) should be open to decrease the influence of input clock noise to output signal waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so. 2. Inverters shown in the above application circuit example are the 74AC04. 3. B1 to B6 in the application circuit example are shown in the figure below.
B1-B6 EQUIVALENT CIRCUIT +12 V
0.1 F 4.7 k CCD VOUT 110 2SA1005 1 k
2SC945
47
+
47 F/25 V
Data Sheet S15417EJ2V0DS
19
PD3728DZ
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 36-PIN CERAMIC DIP (15.24 mm (600))
94.000.7 46.000.5 3.000.08 1.000.08 11.000.15
13.000.5 14.66 4
35.000.6 1 The 1st valid pixel index mark
1.00 (6.00) 2.80.08 1.27 4.850.38 (2.6) 3 (2.8)
0.460.05 24.130.2 20.320.13 48.260.4
2.54 20.320.13 1.000.2 4.000.2 (17.09 MAX.) (15.24 MIN.) 2 3.40.3 0.250.05
Name Glass cap
1 2 3 4
Dimensions 93.0 x 9.0 x 1.1
Refractive index 1.5
1st valid pixel Center of package The bottom of package The surface of the chip The surface of the chip The surface of the glass cap The tolerance of package dimension 0.25 : less than 10mm from W/F edge 0.50 : equal or more than 10mm from W/F edge
36D-1CCD-PKG2-4
20
Data Sheet S15417EJ2V0DS
PD3728DZ
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device
PD3728DZ : CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600))
Process Partial heating method Conditions Pin temperature : 300 C or below, Heat time : 3 seconds or less (per pin)
Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the glass cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may have deleterious effects on prevention of glass cap soiling and heat resistance. So the method cannot be guaranteed.
Data Sheet S15417EJ2V0DS
21
PD3728DZ
NOTES ON HANDLING THE PACKAGES
1 MOUNTING OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with glass cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating For this product, the reference value for the three-point bending strength Note is 180 [N] (at distance between supports: 70 mm). Avoid imposing a load, however, on the inside portion as viewed from the face on which the window (glass) is bonded to the package body (ceramic). Note Three-point bending strength test Distance between supports: 70 mm, Support R: R 2 mm, Loading rate: 0.5 mm/min. Load Load
70 mm
70 mm
2 GLASS CAP
Don't either touch glass cap surface by hand or have any object come in contact with glass cap surface. Care should be taken to avoid mechanical or thermal shock because the glass cap is easily to damage. For dirt stuck through electricity ionized air is recommended.
22
Data Sheet S15417EJ2V0DS
PD3728DZ
NOTES ON HANDLING THE PACKAGES
3 OPERATE AND STORAGE ENVIRONMENTS
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
4 ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. 2. 3. 4. 5. Ground the tools such as soldering iron, radio cutting pliers of or pincer. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. Either handle bare handed or use non-chargeable gloves, clothes or material. Ionized air is recommended for discharge when handling CCD image sensor. For the shipment of mounted substrates, use box treated for prevention of static charges.
6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 M.
Data Sheet S15417EJ2V0DS
23
PD3728DZ
[MEMO]
24
Data Sheet S15417EJ2V0DS
PD3728DZ
[MEMO]
Data Sheet S15417EJ2V0DS
25
PD3728DZ
[MEMO]
26
Data Sheet S15417EJ2V0DS
PD3728DZ
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S15417EJ2V0DS
27
PD3728DZ
* The information in this document is current as of October, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

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